Presently there is a great deal of work being done on the use of a damascene metal scheme, whereby copper is used to provide a low-resistance, metal interconnect, or power buss, on a semiconductor device. This approach is being used for high-current, high-power devices, as well as for high-frequency devices, to lower their interconnect sheet resistance and RC time-constant, to improve speed. The damascene metal scheme is solely an interconnect scheme, and does not improve the parameters or performance of the individual devices. In addition, it is costly in terms of both equipment requirements and process requirements.
What is described here is an approach that reduces the resistance of interconnects and the RC time-constants, while providing improved device parameters and performance, using standard metallization with fewer process steps, and at less cost. This approach results in reduced die size, with the various advantages associated with a smaller die for a given function.